1. Field of the Invention
The invention relates to a semiconductor storage device and a read voltage correction method for use with the storage device, which is, for example, a NAND type flash memory.
2. Description of the Related Art
Evaluation of the read disturb characteristic of NAND type flash memories (chips) on the same semiconductor wafer using the same read voltage reveals that the measurement of the read disturb characteristic varies from chip to chip (see, for example, JP-A 2002-016154 (KOKAI); corresponding to U.S. Pat. No. 6,933,914). This is expected to be attributed to memory characteristic variations resulting from various variations in processing during the manufacturing process. With the NAND type flash memories in particular, the coupling ratio and the neutral threshold of memory cells greatly affect the electric field strength in the tunnel insulating film when a read voltage (Vread) is being applied, which has a great influence upon the read disturb characteristic. Thus, the amounts of leakage current which occurs when the same read voltage is applied depend greatly upon these and influence the read disturb characteristic.
Thus, setting the read voltage Vread to a value common to all the semiconductor chips of a semiconductor wafer gives rise to variations in the amount of leakage current in the tunnel insulating film due to variations in the coupling ratio and neutral threshold, causing the read disturb characteristic to vary from chip to chip.
On the other hand, with present-day manufacturing process technology, it is practically impossible to obtain such precision that influence on variations in read disturb characteristic can be neglected.
With the conventional semiconductor storage devices, as described above, a read operation is performed on the basis of a common read voltage Vread. That is, no read operation is performed using a read voltage corrected so that the read disturb characteristic is optimized for each semiconductor chip. For this reason, the read disturb characteristic is not optimized and the number of fail bits increases, lowering the reliability.
In addition, in the conventional method of examination of semiconductor storage devices, the read voltage Vread is not corrected for each semiconductor chip so as to optimize the read disturb characteristic of each semiconductor chip.
For this reason, when a fixed common read voltage is used for all the semiconductor chips in a semiconductor wafer, faulty chips which fail to meet the standard read disturb characteristic increase in number and proper chips obtained from the wafer decrease in number, lowering the manufacturing yield.